The present invention relates to a semiconductor memory, and more particularly, it relates to a DRAM (dynamic random access memory).
U.S. Pat. No. 5,923,593 discloses a dual-port DRAM cell. According to the disclosure of this patent, each DRAM cell is a two-transistor-one-capacitor (2Tr1C) type cell composed of two access transistors and one data storage capacitor. Assuming that two ports used for making accesses to the data storage capacitor of this DRAM cell are respectively designated as an A port and a B port, the two access transistors are respectively designated as an A port access transistor and a B port access transistor. The A port access transistor has a source connected to one electrode of the data storage capacitor, a gate connected to an A port word line and a drain connected to an A port bit line. The B port access transistor has a source connected to the identical electrode of the data storage capacitor, a gate connected to a B port word line and a drain connected to a B port bit line. The other electrode of the data storage capacitor is connected to a constant supply voltage. This cell configuration enables fast overlapping accesses by utilizing the A port and the B port. For example, while precharging the A port bit line, data can be read or written through the B port.
The above-described U.S. patent also discloses a semiconductor memory including first, second and third memory cell arrays. Each memory cell array is a 2Tr1C type memory cell array including a plurality of DRAM cells each having the aforementioned configuration. An A port sense amplifier circuit is disposed between the first memory cell array and the adjacent second memory cell array, and a B port sense amplifier circuit is disposed between the second memory cell array and the adjacent third memory cell array. The A port sense amplifier circuit is connected to A port bit lines of the first memory cell array and to A port bit lines of the second memory cell array respectively forming pairs with the A port bit lines of the first memory cell array. Since read accesses are never made simultaneously to the first memory cell array and the second memory cell array, the A port sense amplifier circuit can differentially amplify a data signal appeared on an A port bit line of the first or second memory cell array without a fail. On the other hand, the B port sense amplifier circuit is connected to B port bit lines of the second memory cell array and B port bit lines of the third memory cell array respectively forming pairs with the B port bit lines of the second memory cell array. In other words, this semiconductor memory employs what is called an open bitline architecture. Both the A port sense amplifier circuit and the B port sense amplifier circuit are open bitline type sense amplifier circuits.
Data stored in the second memory cell array can be read through the A port sense amplifier circuit disposed on the side of the first memory cell array or through the B port sense amplifier circuit disposed on the side of the third memory cell array. However, the B ports cannot be accessed in the first memory cell array disposed at one end and the A ports cannot be accessed in the third memory cell array disposed at the other end. Therefore, according to this U.S. patent, an open bitline type B port sense amplifier circuit is disposed, for example, outside the first memory cell array and a dummy array is disposed outside this B port sense amplifier circuit. Thus, the B ports of the first memory cell array can be accessed, whereas the dummy array cannot be accessed.
In other words, the dummy array used in this conventional semiconductor memory merely provides reference bit lines to the bit lines of the adjacent memory cell array. Thus, although the dummy array disposed at the end is a 2Tr1C type array including a plurality of dual-port DRAM cells similarly to the essential memory cell arrays, no port of the dummy array can be accessed, which is ineffectual.
An object of the invention is utilizing, for data storage, a dummy array provided in a conventional semiconductor memory having the open bitline architecture, so as to increase usable memory capacity.
In order to achieve the object, the first semiconductor memory of this invention is obtained by replacing the conventional dummy array with an array having both the open bitline architecture and a folded bitline architecture. Specifically, a folded bitline type sense amplifier circuit is provided outside the conventional 2Tr1C type dummy array and the conventional dummy array is provided with word lines so as to be utilized as an end memory cell array.
Specifically, the first semiconductor memory of this invention includes a first memory cell array including first memory cells; first word lines extending into the first memory cell array; a second memory cell array including second memory cells and disposed adjacent to the first memory cell array; second word lines extending into the second memory cell array; a first sense amplifier circuit disposed between the first memory cell array and the second memory cell array; and a second sense amplifier circuit disposed on a side of the second memory cell array opposite to the first sense amplifier circuit. The first sense amplifier circuit is an open bitline type sense amplifier circuit connected to first bit lines extending into the first memory cell array and to second bit lines respectively forming pairs with the first bit lines and extending into the second memory cell array. The second sense amplifier circuit is a folded bitline type sense amplifier circuit connected to third bit lines extending into the second memory cell array and fourth bit lines respectively forming pairs with the third bit lines and extending into the second memory cell array. Each of the first memory cells is a 2Tr1C type cell including a first transistor having a drain connected to one of the first bit lines and a gate connected to one of the first word lines; a second transistor having a source connected to a source of the first transistor and a gate connected to another of the first word lines; and a first data storage capacitor having two electrodes one of which is connected to the sources of the first and second transistors. Each of the second memory cells is also a 2Tr1C type cell including a third transistor having a drain connected to one of the second bit lines and a gate connected to one of the second word lines; a fourth transistor having a drain connected to one of the third or fourth bit lines, a source connected to a source of the third transistor and a gate connected to another of the second word lines; and a second data storage capacitor having two electrodes one of which is connected to the sources of the third and fourth transistors.
Alternatively, the second semiconductor memory of this invention is obtained by replacing each 2Tr1C type cell of the conventional dummy array with two 1Tr1C type cells (each composed of one access transistor and one data storage capacitor), replacing the dummy array with an array having both the open bitline architecture and the folded bitline architecture and providing the dummy array with word lines. Thus, the conventional dummy array can be utilized as an end memory cell array.
Specifically, the second semiconductor memory of this invention includes a first memory cell array including first memory cells; first word lines extending into the first memory cell array; a second memory cell array including second memory cells and third memory cells and disposed adjacent to the first memory cell array; second word lines extending into the second memory cell array; a first sense amplifier circuit disposed between the first memory cell array and the second memory cell array; and a second sense amplifier circuit disposed on a side of the second memory cell array opposite to the first sense amplifier circuit. The first sense amplifier circuit is an open bitline type sense amplifier circuit connected to first bit lines extending into the first memory cell array and to second bit lines respectively forming pairs with the first bit lines and extending into the second memory cell array. The second sense amplifier circuit is a folded bitline type sense amplifier circuit connected to third bit lines extending into the second memory cell array and to fourth bit lines respectively forming pairs with the third bit lines and extending into the second memory cell array. Each of the first memory cells is a 2Tr1C type cell including a first transistor having a drain connected to one of the first bit lines and a gate connected to one of the first word lines; a second transistor having a source connected to a source of the first transistor and a gate connected to another of the first word lines; and a first data storage capacitor having two electrodes one of which is connected to the sources of the first and second transistors. Each of the second memory cells is a 1Tr1C type cell including a third transistor having a drain connected to one of the second bit lines and a gate connected to one of the second word lines; and a second data storage capacitor having two electrodes one of which is connected to a source of the third transistor. Each of the third memory cells is also a 1Tr1C type cell including a fourth transistor having a drain connected to one of the third or fourth bit lines and a gate connected to another of the second word lines; and a third data storage capacitor having two electrodes one of which is connected to a source of the fourth transistor.
In the first or second semiconductor memory, when one of the third bit lines and one of the fourth bit lines together forming a pair are disposed in the second memory cell array in such a manner that one of the second bit lines is sandwiched therebetween, interference between the second bit line and the pair of the third and fourth bit lines can be prevented.
Also, in the first or second semiconductor memory, when each one of the second word lines connected to the gate of the third transistor is kept in an unselected state, the second memory cell array can be always accessed independently of the first memory cell array. Accordingly, such a memory is suitably applied to the case where the first memory cell array is used as a main memory cell array and the second memory cell array is used as a cache memory cell array.
Further alternatively, the third semiconductor memory of this invention is obtained by providing a port connected to the open bitline type sense amplifier circuit in the conventional 2Tr1C type dummy array with word lines. Thus, the conventional dummy array can be utilized as an end memory cell array.
Specifically, the third semiconductor memory of this invention includes a first memory cell array including first memory cells; first word lines extending into the first memory cell array; a second memory cell array including second memory cells and disposed adjacent to the first memory cell array; second word lines extending into the second memory cell array; and a sense amplifier circuit disposed between the first memory cell array and the second memory cell array. The sense amplifier circuit disposed between the first memory cell array and the second memory cell array is an open bitline type sense amplifier circuit connected to first bit lines extending into the first memory cell array and to second bit lines respectively forming pairs with the first bit lines and extending into the second memory cell array. Each of the first memory cells is a 2Tr1C type cell including a first transistor having a drain connected to one of the first bit lines and a gate connected to one of the first word lines; a second transistor having a source connected to a source of the first transistor and a gate connected to another of the first word lines; and a first data storage capacitor having two electrodes one of which is connected to the sources of the first and second transistors. Each of the second memory cells is a memory cell including at least a third transistor having a drain connected to one of the second bit lines and a gate connected to one of the second word lines; and a second data storage capacitor having two electrodes one of which is connected to a source of the third transistor.
In the third semiconductor memory, each of the second memory cells may further include a fourth transistor having a drain connected to a fixed voltage, a source connected to the source of the third transistor and a gate connected to another of the second word lines, and each one of the second word lines connected to the gate of the fourth transistor may be kept in an unselected state. Thus, an unused port of the conventional 2Tr1C type dummy array can be steadily deactivated.